For addressing individual DRAM storage cells in memory chips, bits are applied to the address inputs of the memory chip. To ensure that changes at the address input do not exert any influence on the address after a valid address has been applied, the bit corresponding to the address is latched. As a rule, the signal is converted to CMOS level in this process.
After the latching of the applied bit, the address inputs are disconnected from the other signal path.
A circuit arrangement used in this connection is designated as an address latch. It is used for row addresses, column addresses and in the field of entering data.
European Patent Application EP 0 361 807 A2 discloses a shift register which is controlled with the aid of two phase signals. The shift register comprises two modules which are essentially identical and are interconnected in series between the input and output, each module comprising four transistors and requiring only one phase signal in each case.
A storage arrangement having a voltage generator is disclosed in U.S. Pat. No. 4,156,940. The storage contents are read out in the arrangement via a transistor whose impedance is controlled in the switched-on state via a level which is made available by a voltage divider.
A static MOS latch is disclosed in U.S. Pat. No. 4,754,165. The arrangement comprises an output and an inverted output, which are tapped in each case between two series-connected MOS transistors which are connected in series between the higher voltage level and the lower voltage level. The MOS transistors connected in series are acted upon in each case by an input and an inverted input, with the result that when a signal corresponding to the higher level is present the output is connected to the voltage corresponding to the higher level and the inverted output is simultaneously connected to the voltage corresponding to the lower level, and vice versa.
The older European Patent Application EP 0 478 252 A2 (corresponding to U.S. Pat. No. 5,128,897), which is not a prior publication, discloses a storage arrangement which comprises, inter alia, address latches. An input signal is applied in the address latch via an NOR element to the input of a storage element.